525.712 Advanced Computer Architecture
Spring 2010
Slides
Chapter 1 Figures
Graph of data in Table 1.1 on p. 2
Limits of ILP shown on p.25 of Shen and Lipasti
Chapter 2 Figures
Tables 2.2, 2.3, and 2.4, pp. 63-64, Specification of Instruction Types
Table 2.5: Worst-case penalties due to RAW hazards in the TYP pipeline.
Table 2.6: Worst-case penalties due to RAW hazards in the TYP pipeline when forwarding paths are used.
Table 2.7: Functionality of the MIPS R2000/R3000 five-stage pipeline.
Table 2.8: Functionality of the Intel 486 five-stage pipeline
Table 2.9: Conditional branch penalties considering PC-relative addressing and scheduling penalty slot
Chapter 3 Figures
Table 3.1: Attributes of Memory Hierarchy Components
Table 3.2: Interaction of Cache Organization and Cache Misses
Table 3.3: Correction to Table 3.3: Translatin linear physical adress to DRAM address
Table 3.4: Types of input/output device
Table 3.5: Redundant arrays of inexpensive disks (RAID) levels
Chapter 4 Figures
Chapter 5 Figures
SPEC Benchmarks (CINT92, CFP92)
Chapter 6 Figures
Table 6.1: Dynamic instruction mix of the benchmark set
Table 6.2: Summary of benchmark performance
Table 6.3: Branch prediction data
Table 6.4: Zero bandwidth fetch cycles
Table 6.5: Distribution and average number of branches bypassed
Table 6.6: Summary of average number of buffers used
Table 6.7: Frequency of dispatch stall cycles
Table 6.8: Frequency of issue stall cycles
Table 6.9: Average execution latency (in cycles) in each of the six execution units for the benchmarks
Table 6.10: Cache effect data
Table 6.11: PowerPC 620 versus POWER3 and POWER4
Chapter 7 Figures
Chapter 8 Figures
Table 8.1: ACS-1 Performance Comparison
Table 8.2: Out-of-order execution
Table 8.3: Comparison of POWER processors.
Class discussion questions
Chapter 9 Figures
Table 9.1: Ball and Larus's static branch prediction rules.
Chapter 10 Figures
Chapter 11 Figures
Table 11.1: Some common synchronization primitives
Table 11.2: Various aproaches to resource sharing and context switching.
Table 11.3: Attributes of several implicit multithreading proposals.
Last updated: 23 January 2010